 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 31014hkim 20130905-s00003 no.a2304-1/31 semiconductor components industries, llc, 2014 march, 2014 ver. 1.01 http://onsemi.com lc87f0g08a features ? a 10 ? /20 ? amplifier ? a 8/10-bit high-speed pwm(150khz) ? a reference voltage generator circuit(2v/4v) for an ad converter ? a temperature sensor ? an internal reset circuit ? a 7-channel ad converter with 12-/8-bit resolution selector ? internal oscillation circuits (30khz/1mhz/8mhz) performance ? 83.3ns (12.0mhz) v dd =2.7v to 5.5v ta= ? 40 ? c to + 85 ? c ? 125ns (8.0mhz) v dd =2.0v to 5.5v ta= ? 40 ? c to + 85 ? c ? 250ns (4.0mhz) v dd =1.8v to 5.5v ta= ? 40 ? c to + 85 ? c function descriptions ? ports - i/o ports : 18 - reference voltage outputs : 1 (vref) - power supply pins : 3 (v ss 1, v ss 2, v dd 1) ? timers (3ch) - timer 0 : 16-bit timer/counter with a capture register. - timer 1 : 16-bit timer/counter that supports pwm/toggle outputs - a base timer serving as a realtime clock ? sio (1ch) - sio1 : 8-bit asynchronous/synchronous serial interface ? comparator ? watchdog timer ? frequency tunable 12-bit pwm ? 2ch ? system clock divider function ? cf oscillation circuit, x'tal oscillation circuit ? 15 sources, 10 vectors interrupts ? on-chip debugger function application ? shaver, battery charge control ordering number : ena2304 cmos lsi 8-bit 1-chip microcontroller 8k-byte flash rom / 256-byte ram / 24-pin * this product is licensed from silicon storage technology, inc. (usa). ssop24(225mil) pin assignment (top view) p70/int0/t0lcp/an09 res vss1 cf1/xt1 cf2/xt2 vdd1 p10/so1 p11/si1/sb1 p12/sck1 p13/int4/t1in/an7 p14/int4/t1in/an6 p15/int3/t0in/an5 24 23 22 21 20 19 18 17 16 15 14 13 owp0 p06/t1pwmh p05/t1pwml /cko p04/an4/vcpwm1 p03/an3/vcpwm0 p02/an2/cpim p01/apip p00/apim vref vss2 p17/buz/int1/t0hcp/hpwm2 p16/int2/t0in/cpout/hpwm2 1 2 3 4 5 6 7 8 9 10 11 12 lc87f0g08a ordering information see detailed ordering and shipping informa tion on page 31 of this data sheet.
lc87f0g08a no.a2304-2/31 function details ? flash rom ?? capable of on-board programming with a wide range of supply voltages : 2.2 to 5.5v ?? block-erasable in 128 byte units ?? writes data in 2-byte units ?? 8192 8 bits ? ram ?? 256 9 bits ? bus cycle time ?? 83.3ns ( 12mhz, v dd =2.7v to 5.5v, ta= ? 40 ? c to 85 ? c) ?? 125ns ( 8mhz, v dd =2.0v to 5.5v, ta= ? 40 ? c to 85 ? c) ?? 250ns ( 4mhz, v dd =1.8v to 5.5v, ta= ? 40 ? c to 85 ? c) note : the bus cycle time here refers to the rom read speed. ? minimum instruction cycle time (tcyc) ?? 250ns (12mhz, v dd =2.7v to 5.5v, ta= ? 40 ? c to 85 ? c) ?? 375ns ( 8mhz, v dd =2.0v to 5.5v, ta= ? 40 ? c to 85 ? c) ?? 750ns ( 4mhz, v dd =1,8v to 5.5v, ta= ? 40 ? c to 85 ? c) ? potrs ? normal withstand voltage i/o ports whose i/o direction can be designated in 1-bit units 18(p0n, p1n, p70, cf1, cf2) ? reset pins 1( res ) ? power supply pins 3(v ss 1, v ss 2,v dd 1) ? reference voltage outputs 1(vref) ? dedicated debugger port 1(owp0) ? timers ??? timer 0 : 16-bit timer/counter with 2 capture registers. mode 0 : 8-bit timer with an 8-bit programmabl e prescaler (with two 8- bit capture registers) ? 2 channels mode 1 : 8-bit timer with an 8-bit programmable prescaler (with two 8-b it capture registers) + 8-bit counter (with two 8-bit capture registers) mode 2 : 16-bit timer with an 8-bit programmabl e prescaler (with two 16-bit capture registers) mode 3 : 16-bit counter (with two 16-bit capture registers) ??? timer 1 : 16-bit timer/counter that supports pwm/toggle outputs mode 0 : 8-bit timer with an 8-bit prescal er (with toggle out puts) + 8-bit timer/ counter with an 8-bit pres caler (with toggle outputs) mode 1 : 8-bit pwm with an 8-bit prescaler ? 2 channels mode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order 8 bits) mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs) (lower-order 8 bits may be used as a pwm output) ?? base timer (1) the clock is selectable from the subclock (32.768khz cr ystal oscillation), the low speed rc, system clock, and timer 0 prescaler output. (2) with an 8-bit programmable prescaler (3) interrupts programmable in 5 different time schemes lc87f0g08a no.a2304-3/31 ? sio ?? sio1 : 8-bit asynchronous/synchronous serial interface mode 0 : synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1 : asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2 : bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3 : bus mode 2 (start detect, 8 data bits, stop detect) ? ad converter: ?? ad converter input port with 10 ? /20 ? amplifier (1channel) ?? ad converter input port (7channel) 12-/8-bit resolution selectable ad converter ?? selectable reference voltage source for an ad converter ( selectable from v dd , internal reference voltage generator circuit(vref) .) ? internal reference voltage generator circuit(vref) ?? generates 2.0v/4.0v for ad converter. ? comparator comparator input pin (1 channel) comparator output pin (1 channel) comparator output set high when (comparator input level) < 1.22v comparator output set low when (comparator input level) > 1.22v ? clock output function ?? generates clocks with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillation clock that is selected as the system clock. ? watchdog timer ?? generates an internal reset on an overflow occurring in the timer running on the low-speed rc oscillator clock (approx. 30khz) or subclock. ?? operating mode at standby is selectable from 3 modes (continue counting/suspend operation/suspend counting with the count value retained) lc87f0g08a no.a2304-4/31 ? interrupts ?? 15 sources, 10 vectors 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than th e current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address is given priority. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/bt 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l hpwm2 8 0003bh h or l sio1 9 00043h h or l adc 10 0004bh h or l p0/vcpwm ?? priority levels x > h > l ?? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: up to 128levels (the stack is allocated in ram.) ? high-speed multiplication/division instructions ?? 16 bits ? 8 bits (5 tcyc execution time) ?? 24 bits ? 16 bits (12 tcyc execution time) ?? 16 bits ? 8 bits (8 tcyc execution time) ?? 24 bits ? 16 bits (12 tcyc execution time) ? oscillation circuits ?? internal oscillation circuits 1) low-speed rc oscillation circuit: for system clock (approx.30khz) 2) medium-speed rc oscillation circuit: for system clock (1mhz) 3) hi-speed rc oscillation circuit1: for system clock (8mhz) 4) hi-speed rc oscillation circuit2: for high speed pwm (40mhz) ? system clock divider function ?? can run on low consumption current. ?? minimum instruction cycle select able from 375ns, 750ns, 1.5 ? s, 3.0 ? s, 6.0 ? s, 12.0 ? s, 24.0 ? s, 48.0 ? s, and 96.0 ? s (at 8mhz main clock) ? internal reset circuit ?? power-on reset (por) function 1) por reset is generated only at power-on time. 2) the por release level is 1.67v. ?? low-voltage detection reset (lvd) function 1) lvd and por functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) the use/disuse of the lvd function and the low voltage threshold level can be selected from 7 levels (1.91v, 2.01v, 2.31v, 2.51v, 2.81v, 3.79v and 4.28v), through option configuration. lc87f0g08a no.a2304-5/31 ? standby function halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are three ways of resetting the halt mode. (1) setting the reset pin to the low level (2) having the watchdog timer or lvd function generate a reset (3) having an interrupt generated hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the cf, rc and crystal oscillators automatically stop operation. note: the low-speed rc oscillator is controlled directly by the watchdog timer; its oscillation in the standby mode is also controlled by the watchdog timer. 2) there are four ways of resetting the hold mode: (1) setting the reset pin to the lower level (2) having the watchdog timer or lvd function generate a reset (3) having an interrupt source established at one of the int0, int1, int2 and int4 pins * int0 and int1 can be used in the level sense mode only. (4) having an interrupt source established at port 0. x'tal hold mode: suspends instruction execution and the oper ation of the peripheral circuits except the base timer. (when x?tal oscillation or low-speed rc oscillation is selected). 1) the cf, low-speed, and medium-speed rc oscillators automatically stop operation. note: the low-speed rc oscillator is controlled directly by the watchdog timer; its oscillation in the standby mode is also controlled by the watchdog timer. note: if the base timer is run with low-speed rc oscillation selected as the base timer input clock source and the x?tal hold mode is entered, the low-speed rc oscillato r retains the state that is established when the x?tal hold mode is entered. 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are five ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) having the watchdog timer or lvd function generate a reset (3) having an interrupt source established at one of the int0, int1, int2, and int4 pins * int0 and int1 can be used in the level sense mode only. (4) having an interrupt source established at port 0 (5) having an interrupt source established in the base timer circuit ? vcpwm: frequency tunable 12-bit pwm 2ch ? high speed pwm (hpwm2) 8-/10- bits pwm 1ch 1) the pwm clock is selectable from system clock and hi-speed rc2 (40mhz) 2) the pwm type is selectable from 8 bits(normal mode) and 10 bits( additive puls mode). ? temperature sensor ?? senseor voltage can be comapred by the ad converter. ? on-chip debugger function ?? supports software debugging with the ic mounted on the target board. ?? provides 1 channel of on-chip debugger pin. owp0 ? data security function ?? protects the program data stored in flash memory from unauthorized read or copy. note: this data security function does not necessarily provide absolute data security. ? package form ?? ssop24 (225mil): lead-fre e and halogen-free type lc87f0g08a no.a2304-6/31 ? development tools ?? on-chip debugger: tcb87 type c (1-wire interface cable) + lc87f0g08a ? programming boards package programming boards ssop24(225mil) w87f0gs ? flash programmer maker model supported version device flash support group, inc. (fsg) single programmer af9709c rev 03.28 or later 87f008su flash support group, inc. (fsg) + our company (note 1) onboard single/gang programmer af9101/af9103(main unit) (fsg models) (note 2) - sib87 type c(inter face driver) (our company model) our company single/gang programmer skk type b / skk type c application version 1.08 or later chip data version 2.46 or later lc87f0g08 onboard single/gang programmer skk-dbg type c for information about af-series : flash support group, inc. tel: +81-53-459-1050 e-mail: sales@j-fsg.co.jp note1: on-board-programmer from fsg (af9101/af9103) and serial interface driv er from our company (sib87 type c) together can give a pc-less, standalone on-board-programming capabilities. note2: it needs a special programming devices and applications depending on the use of programming environment. please ask fsg or our comp any for the information. lc87f0g08a no.a2304-7/31 package dimensions unit : mm ssop24 (225mil) case 565ar issue a xxxxxxxxxx ymddd xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. soldering footprint* note: the measurements are not to guarantee but for reference only. (unit: mm) *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 1.0 5.80 0.32 0.50 lc87f0g08a no.a2304-8/31 pin assignment ssop24(225mil) "lead-/halogen-free type" ssop24 name ssop24 name 1 p70/int0/t0lcp/an09 13 p16/int2/t0in/cpout/hpwm2 2 res 14 p17/buz/int1/t0hcp/hpwm2 3 v ss 1 15 v ss 2 4 cf1/xt1 16 vref 5 cf2/xt2 17 p00/apim 6 v dd 1 18 p01/apip 7 p10/so1 19 p02/an2/cpim 8 p11/si1/sb1 20 p03/an3/vcpwm0 9 p12/sck1 21 p04/an4/vcpwm1 10 p13/int4/t1in/an7 22 p05/t1pwml/cko 11 p14/int4/t1in/an6 23 p06/t1pwmh 12 p15/int3/t0in/an5 24 owp0 p70/int0/t0lcp/an09 res v ss 1 cf1/xt1 cf2/xt2 v dd 1 p10/so1 p11/si1/sb1 p12/sck1 p13/int4/t1in/an7 p14/int4/t1in/an6 p15/int3/t0in/an5 24 23 22 21 20 19 18 17 16 15 14 13 owp0 p06/t1pwmh p05/t1pwml /cko p04/an4/vcpwm1 p03/an3/vcpwm0 p02/an2/cpim p01/apip p00/apim vref v ss 2 p17/buz/int1/t0hcp/hpwm2 p16/int2/t0in/cpout/hpwm2 1 2 3 4 5 6 7 8 9 10 11 12 lc87f0g08a lc87f0g08a no.a2304-9/31 system block diagram interrupt control standby control ir pla flash rom pc bus interface port0 port1 timer0 adc int0-4 (int3 with noise filter) acc b register c register psw rar ram stack pointer alu reset circuit (lvd/por) wdt (low speed rc) reset control res on-chip debugger 10x/20x amplifier (1 channel) vref + - sio1 port7 clock generator medium speed rc high speed rc cf/xt low speed rc base timer timer1 comparator vcpwm hpwm2 temperature sensor high speed rc2 lc87f0g08a no.a2304-10/31 pin description pin name i/o description option v ss 1 - - power supply pin no v dd 1 - + power supply pin no v ss 2 - - power supply pin no vref i/o reference voltage output(2.0v/4.0v) or external input no owp0 i/o on-chip debugger pin no port 0 i/o ? 7-bit i/o port ? i/o specifiable in 1-bit units. ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p00 (an0), p01 (an1): ad converter input port with 10x/20x operational amplifier p02: ad converter input port (a n2) / comparator input (cpim) p03: ad converter input port (an3) / vcpwm0 output p04: ad converter input port (an4) / vcpwm1 output p05: timer 1 pwml output / system clock output p06: timer 1 pwmh output p07: on-chip debugger pin (owp0) yes p00 to p06 port 1 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units. ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p10: sio1 data output p11: sio1 data in put/bus input/output p12: sio1 clock input/output p13: int4 input/hold release input/timer 1 ev ent input/timer 0l capture input/ timer 0h capture input/ ad converter input port (an7) p14: int4 input/hold release input/timer 1 ev ent input/timer 0l capture input/ timer 0h capture input/ ad converter input port (an6) p15: int3 input(with noise filter)/timer 0 event input/timer 0h capture input/ ad converter input port (an5) p16: int2 input/hold release input/timer 0 event input/ timer 0l capture input/hpwm2 output p17: beeper output/int1 input/hold release i nput/timer 0h capture input/hpwm2 output interrupt acknowledge type yes p10 to p15 rising falling rising & falling h level l level int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable int4 enable enable enable disable disable continued on next page. lc87f0g08a no.a2304-11/31 continued from preceding page. pin name i/o description option port 7 i/o ? 1-bit i/o port ? i/o specifiable ? pull-up resistors can be turned on and off. ? pin functions p70 : int0 input/hold release input/timer 0l capture input/ad converter input port (an9) interrupt acknowledge type rising falling rising & falling h level l level int0 enable enable disable enable enable no p70 res i external reset input/internal reset output pin yes internal pullup on/off cf1/xt1 i/o ? ceramic oscillator/32.768khz crystal oscillator input pin ? pin functions ? 1-bit i/o port ? i/o specifiable (only nch-open drain) no cf2/xt2 i/o ? ceramic oscillator/32.768khz crystal oscillator output pin ? pin functions ? 1-bit i/o port ? i/o specifiable no owp0 i/o on-chip debugger pin no lc87f0g08a no.a2304-12/31 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor p00 to p06 1 bit 1 cmos programmable 2 nch-open drain programmable p10 to p17 1 bit 1 cmos programmable 2 nch-open drain programmable cf1/xt1 - no nch-open drain when general i/o port is selected. no cf2/xt2 - no cmos / nch-open drain when general i/o port is selected.(programmable) no p70 - no nch-open drain programmable user option table option name option type flash version opti on selected in units of option selection port output form p00 to p06 enable 1 bit cmos nch-open drain p10 to p17 enable 1 bit cmos nch-open drain program start address - enable - 00000h or 01e00h when protected area 1) is selected 00000h when either of protected area 2), 3) or 4) is selected protected area (note1) - enable - 1) 1800h-1fffh 2) 0000h-1dffh,1f00h-1fffh 3) 0000h-1cffh,1f00h-1fffh 4) 0000h-1affh,1f00h-1fffh reset pin internal pullup on/off enable - on off low-voltage detection reset function detect function enable - enable: use disable: not used detect level enable - 7-level power-on reset function power-on reset level enable - 1-level note1: onboard programming inhbited address lc87f0g08a no.a2304-13/31 recommended unused pin connections port name recommended unused pin connections board software p00 to p07 open output low p10 to p17 open output low p70 open output low cf1/xt1 open general i/o port output low cf2/xt2 open general i/o port output low owp0 pulled low with a 100k ? resistor - on-chip debugger pin connection requirements for the treatment of the on-chip debugger pins, refer to the separately available documents entitled ?rd87 on-chip debugger installation manual? power pin treatment recommendations (v dd 1, v ss 1) connect bypass capacitors that meet the following conditions between the v dd 1 and v ss 1 pins: ?? connect among the v dd 1 and v ss 1 pins and bypass capacitors c1 and c2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as equal as possible (l1=l1?, l2=l2?). ?? connect a large-capacity cap acitor c1 and a small-capacity capacitor c2 in parallel. the capacitance of c2 should be approximately 0.1 ? f. v ss 1 v dd 1 l1? l2? l1 l2 c1 c2 lc87f0g08a no.a2304-14/31 absolute maximum ratings at ta = 25 ? c, v ss 1 = v ss 2 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit maximum supply voltage v dd max v dd 1 -0.3 to +6.5 v input/output voltage vio port0,1 port7 cf1,cf2, res -0.3 to v dd +0.3 high level output current peak output current ioph(1) port0 port1 cf2 ? when cmos output type is selected ? per 1 applicable pin -10 ma average output current (note 1-1) iomh(1) port0 port1 cf2 ? when cmos output type is selected ? per 1 applicable pin -7.5 total output current ioah(1) port0,1, cf2 total current of all applicable pins -30 low level output current peak output current iopl(1) port0 ? per 1 applicable pin 20 iopl(2) port1 ? per 1 applicable pin 20 iopl(3) port7,cf1,cf2 ? per 1 applicable pin 10 average output current (note 1-1) ioml(1) port0 ? per 1 applicable pin 15 ioml(2) port1 ? per 1 applicable pin 15 ioml(3) port7,cf1,cf2 ? per 1 applicable pin 7.5 total output current ioal(1) port0,1,7, cf1,cf2 total current of all applicable pins 80 allowable power dissipation pdmax(1) ssop24(225mil) ta=-40 to + 85 ? c package with thermal resistance board (note 1-2) 260 mw operating ambient temperature topr -40 +85 ? c storage ambient temperature tstg -55 +125 note 1-1: the average output current is an average of current values measured over 100ms intervals. note 1-2: semi standards ther mal resistance board (size: 76.1 ? 114.3 ? 1.6tmm, glass epoxy) is used. stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. lc87f0g08a no.a2304-15/31 allowable operating conditions at ta = -40 ? c to +85 ? c, v ss 1 = v ss 2 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit operating supply voltage (note 2-1) vdd(1) vdd1 0.245 ? s ? tcyc ? 200 ? s 2.7 5.5 v vdd(2) 0.367 ? s ? tcyc ? 200 ? s 2.0 5.5 vdd(3) 0.735 ? s ? tcyc ? 200 ? s 1.8 5.5 memory sustaining supply voltage vhd vdd1 ram and register contents sustained in hold mode. 1.6 high level input voltage vih(1) port 0,1 p70 1.8 to 5.5 0.3v dd +0.7 v dd vih(4) cf1,cf2, res 1.8 to 5.5 0.75v dd v dd low level input voltage vil(1) port 0,1 p70 4.0 to 5.5 v ss 0.1v dd +0.4 1.8 to 4.0 v ss 0.2v dd vil(4) cf1,cf2, res 1.8 to 5.5 v ss 0.25v dd instruction cycle time (note 2-2) tcyc (note 2-2) 2.7 to 5.5 0.245 200 ? s 2.0 to 5.5 0.367 200 1.8 to 5.5 0.735 200 external system clock frequency fexcf cf1 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty=50 ? 5% 2.7 to 5.5 0.1 12 mhz 2.2 to 5.5 0.1 8 oscillation frequency range (note 2-3) fmcf(1) cf1,cf2 when 12m hz ceramic oscillation see fig. 1. 2.7 to 5.5 12 mhz fmcf(2) cf1,cf2 when 8m hz ceramic oscillation see fig. 1. 2.2 to 5.5 8 fmcf(3) cf1,cf2 when 4m hz ceramic oscillation see fig. 1. 1.8 to 5.5 4 fmfrc(1) internal high-speed rc oscillation ta=-10 ? c to +85 ? c (note 2-4) 1.8 to 5.5 7.76 8.0 8.24 fmfrc(2) internal high-speed rc oscillation ta=-40 ? c to +85 ? c (note 2-4) 1.8 to 5.5 7.60 8.0 8.40 fmrc internal medium-speed rc oscillation 1.8 to 5.5 0.5 1.0 2.0 fmsrc internal low-speed rc oscillation (note 2-5) 1.8 to 5.5 27 30 33 khz fsx?tal xt1,xt2 32.768khz crystal oscillation see fig. 2. 1.8 to 5.5 32.768 khz fmpwmrc internal high-speed rc oscillation for hpwm2 2.7 to 5.5 38 40 42 mhz oscillation stabilization time tmscf cf1,cf2 ? when oscillation circuit is switched from ?oscillation stopped? to ?oscillation enabled? . ? see fig. 3. see table 1 ? s tmsfrc (note 2-4) 1.8 to 5.5 100 tmspwmr c 1.8 to 5.5 100 tmsrc 1.8 to 5.5 0 tmssrc (note2-5) 1.8 to 5.5 1 ms tmsx?tal xt1,xt2 see table 2 note 2-1: v dd must be held greater than or equal to 2.7v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see tables 1 and 2 for the oscillation constants. note 2-4: an oscillation stabilization time of 100 ? s or longer must be provided be fore switching the system clock source after the state of the high-speed rc oscillati on circuit is switched from ?oscillation stopped? to ?oscillation enabled? . note 2-5: an oscillation stabilization time of 1ms or longer must be provided before switching the system clock source after the state of the low-speed rc oscillation circuit is switched from ?oscillation stopped? to ?oscillation enabled? . functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility. lc87f0g08a no.a2304-16/31 electrical characteristics at ta = -40 ? c to +85 ? c, v ss 1 = v ss 2 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high level input current i ih (1) port 0,1, port 7, res output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 1.8 to 5.5 1 ? a i ih (2) cf1 v in =v dd 1.8 to 5.5 15 low level input current i il (1) port 0,1, port 7, res output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 1.8 to 5.5 -1 i il (2) cf1 v in =v ss 1.8 to 5.5 -15 high level output voltage v oh (1) port 0,1, cf2 i oh =-1ma 4.5 to 5.5 v dd -1 v v oh (2) i oh =-0.2ma 1.8 to 5.5 v dd -0.4 low level output voltage v ol (1) port 0,1, p70,cf1,cf2 i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.0ma 1.8 to 5.5 0.4 pull-up resistance rpu(1) port 0,1, p70 v oh =0.9v dd 4.5 to 5.5 15 35 80 k ? rpu(2) 1.8 to 4.5 18 50 230 rpu(3) res 1.8 to 5.5 300 400 500 hysteresis voltage vhys(1) port 0,1, p70 res 2.7 to 5.5 0.1v dd v 1.8 to 5.5 0.07v dd pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 ? c 1.8 to 5.5 10 pf product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions. lc87f0g08a no.a2304-17/31 sio1 serial i/o characteristics (note 4-1) parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(1) sck1(p12) ? see fig. 5. 1.8 to 5.5 2 tcyc low level pulse width tsckl(1) 1 high level pulse width tsckh(1) 1 output clock frequency tsck(2) sck1(p12) ? cmos output type selected ? see fig. 5. 1.8 to 5.5 2 low level pulse width tsckl(2) 1/2 tsck high level pulse width tsckh(2) 1/2 serial input data setup time tsdi(1) si1(p11), sb1(p11) ? specified with respect to rising edge of sioclk. ? see fig. 5. 1.8 to 5.5 0.05 ? s data hold time thdi(1) 0.05 serial output output delay time tddo(1) so1(p10), sb1(p11) ? specified with respect to falling edge of sioclk ? specified as the time up to the beginning of output change in open drain output mode. ? see fig. 5. 1.8 to 5.5 (1/3)tcyc +0.08 note 4-1: these specifications are theoretical values. ma rgins must be allowed accordin g to the actual operating conditions. pulse input conditions at ta = -40 ? c to +85 ? c, v ss 1 = v ss 2 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high/low level pulse width tpih(1) tpil(1) int0(p70), int1(p71), int2(p16), int4(p13, p14) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 1.8 to 5.5 1 tcyc tpih(2) tpil(2) int3(p15) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 1.8 to 5.5 2 tpih(3) tpil(3) int3(p15) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 1.8 to 5.5 64 tpih(4) tpil(4) int3(p15) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 1.8 to 5.5 256 tpil(5) res ? resetting is enabled. 1.8 to 5.5 200 ? s lc87f0g08a no.a2304-18/31 ad converter characteristics at v ss 1 = v ss 2 = 0v <12bits ad converter mode/ta = -40 ? c to +85 ? c > parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an2(p02) an3(p03) an4(p04) an5(p15) an6(p14) an7(p13) an9(p70) (note 6-3) 1.8 to 5.5 12 bit absolute accuracy et (note 6-1) 1.8 to 5.5 ? 16 lsb conversion time tcad ? see conversion time calculation method. (note 6-2) 2.7 to 5.5 32 115 ? s 2.2 to 5.5 134 215 1.8 to 5.5 400 430 analog input voltage range vain(1) when v dd is selected 1.8 to 5.5 v ss v dd v vain(2) when internal vref=4v is selected. vref ? v dd 4.3 to 5.5 v ss vref when internal vref=2v is selected vref ? v dd 2.3 to 3.6 v ss vref analog port input current iainh vain=v dd 1.8 to 5.5 1 ? a iainl vain=v ss 1.8 to 5.5 -1 <8bits ad converter mode/ta = -40 ? c to +85 ? c > parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an2(p02) an3(p03) an4(p04) an5(p15) an6(p14) an7(p13) an9(p70) (note 6-3) 1.8 to 5.5 8 bit absolute accuracy et (note 6-1) 1.8 to 5.5 ? 1.5 lsb conversion time tcad ? see conversion time calculation method. (note 6-2) 2.7 to 5.5 20 90 ? s 2.2 to 5.5 80 135 1.8 to 5.5 245 265 analog input voltage range vain(1) when v dd is selected 1.8 to 5.5 v ss v dd v vain(2) when internal vref=4v is selected. vref ? v dd 4.3 to 5.5 v ss vref when internal vref=2v is selected. vref ? v dd 2.3 to 3.6 v ss vref analog port input current iainh vain=v dd 1.8 to 5.5 1 ? a iainl vain=v ss 1.8 to 5.5 -1 lc87f0g08a no.a2304-19/31 lc87f0g08a no.a2304-20/31 10x/20x amplifier characteristics at ta = -40 ? c to +85 ? c, v ss 1 = v ss 2 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit 20x amplifier gain apgain20 see fig7 p00/apim p01/apip ? ta=-40 to +85 ? c 1)apdir=0 & gain20=1. ? p01=0v,p00 ? 0v or p00=0v,p01 ? 0v 2)apdir=1 & gain20=1. ? p01=0v,p00 ? 0v or p00=0v,p01 ? 0v 4.3 to 5.0 20 20x amplifier offset vapio20 200 600 mv 20x amplifier input voltage range vapim20-1 p00/apim 1) p01/apip=0v -0.17 0 v vapip20-1 p01/apip p00/apim=0v 0 0.17 vapim20-2 p00/apim 2) p01/apip=0v 0 0.17 v vapip20-2 p01/apip p00/apim=0v -0.17 0 10x amplifier gain apgain10 see fig7 p00/apim p01/apip ? ta=-40 to +85 ? c 3)apdir=0 & gain20=0. ? p01=0v,p00 ? 0v or p00=0v,p01 ? 0v 4)apdir=1 & gain20=0. ? p01=0v,p00 ? 0v or p00=0v,p01 ? 0v 10 10x amplifier offset vapio10 100 300 mv 10x amplifier input voltage range vapim10-3 p00/apim 3) p01/apip=0v -0.24 0 v vapip10-3 p01/apip p00/apim=0v 0 0.24 vapim10-4 p00/apim 4) p01/apip=0v 0 0.24 v vapip10-4 p01/apip p00/apim=0v -0.24 0 amplifier input port input current iapinl p00/apim p00/apim=v ss -0.2v -1 ? a iapinh p01/apip p01/apip=v dd 1 operation stabilization time (note 8-1) tapw 20 ? s note 8-1: refers to the interval between the time apon is set to 1 and the time operation gets stabilized. lc87f0g08a no.a2304-21/31 comparator characteristics at ta = -40 ? c to +85 ? c, v ss 1 = v ss 2 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit comparator threshold voltage (note 9-1) vcmvt p02/cpim 2.5 to 5.5 1.12 1.22 1.32 v input voltage range vcmin 2.5 to 5.5 v ss v dd v offset voltage voff ? within input voltage range 2.5 to 5.5 10 30 mv response time trt ? within input voltage range ? input amplitude =100mv ? overdrive=50mv 2.5 to 5.5 200 600 ns operation stabilization time (note 9-2) tcmw 2.5 to 5.5 1.0 ? s note 9-1: comparator output=high le vel when (p02/cpim voltage) < vcmvt comparator output=low level when (p02/cpim voltage) > (vcmvt +voff) note 9-2: refers to the interval between the time cpon is set to 1 and the time operation gets stabilized. temperature sensor characteristics at ta = -40 ? c to +85 ? c, v ss 1 = v ss 2 = 0v <4-diode mode> parameter symbol pin/remarks conditions specification v dd [v] min typ max unit output voltage votmp4(1) ta=-40 ? c 5.0 3.23 3.25 3.27 v votmp4(2) ta=+25 ? c 5.0 2.75 2.77 2.80 votmp4(3) ta=+85 ? c 5.0 2.28 2.31 2.34 sensitivity vsen4 ta=-40 to +85 ? c 3.5 to 5.5 -7.63 -7.54 -7.45 mv/ ? c absolute accuracy (note 10-1) (note 10-2) ettmp4 vref=4[v] ta=(6010) ? c (note 10-3) 3.5 to 5.5 2.5 5 ? c ta=-40 to +85 ? c 3.5 to 5.5 5 10 <2-diode mode> parameter symbol pin/remarks conditions specification v dd [v] min typ max unit output voltage votmp2(1) ta=-40 ? c 3.3 1.61 1.63 1.64 v votmp2(2) ta=+25 ? c 3.3 1.37 1.39 1.40 votmp2(3) ta=+85 ? c 3.3 1.14 1.16 1.17 sensitivity vsen2 ta=-40 to +85 ? c 2.0 to 5.5 -3.81 -3.77 -3.72 mv/ ? c absolute accuracy (note 10-1) (note 10-2) ettmp2 vref=2[v] ta=(6010) ? c (note 10-4) 2.0 to 5.5 2.5 5 ? c ta=-40 to +85 ? c 2.0 to 5.5 5 10 note 10-1: there are cases wh en the absolute accuracy specification valu e is exceeded when a large current flows through the ports. note 10-2: including error of ad converter. note 10-3: when using the temperature sensor 60 ? c 2-diodes reference register d2tl/ d2th. note 10-4: when using the temperature sensor 60 ? c 4-diodes reference register d4tl/ d4th. lc87f0g08a no.a2304-22/31 power-on reset (por) characteristics at ta = -40 ? c to +85 ? c, v ss 1 = v ss 2 = 0v parameter symbol pin / remarks conditions specification option selected voltage min typ max unit por release voltage porrl option selected (note 11-1) 1.67v 1.10 1.79 v detection voltage unpredictable area pouks see fig. 8. (note 11-2) 0.7 0.95 power supply rise time poris power startup time from vdd=0v to 1.6v 100 ms note 11-1: the por release voltage can be selected wh en the low-voltage detection feature is deselected. note 11-2: there is an unpred ictable area before the transistor starts to turn on. low voltage detection reset (lvd) characteristics at ta = -40 ? c to +85 ? c, v ss 1= v ss 2= 0v parameter symbol pin / remarks conditions specification option selected voltage min typ max unit lvd reset voltage (note 12-2) lvdet option selected see fig. 9. (note 12-1) (note 12-3) 1.91v 1.81 1.91 2.01 v 2.01v 1.91 2.01 2.11 2.31v 2.21 2.31 2.41 2.51v 2.41 2.51 2.61 2.81v 2.71 2.81 2.93 3.79v 3.69 3.79 3.92 4.28v 4.18 4.28 4.41 lvd voltage hysteresis lvhys 1.91v 55 mv 2.01v 55 2.31v 55 2.51v 55 2.81v 60 3.79v 65 4.28v 65 detection voltage unpredictable are a lvuks see fig. 9. (note 12-4) 0.7 0.95 v minimum low voltage detection width (response sensitivity) tlvdw lvdet-0.5v see fig. 10. 0.2 ms note 12-1: the lvd reset voltage can be selected from 7 le vels when the low-voltage detection feature is selected. note 12-2: the hysteresis voltage is not included in the lvd reset voltage specification value. note 12-3: there are cases when the lvd reset voltage specification value is exceeded when a greater change in the output level or large current is applied to the port. note 12-4: there is an unpr edictable area before the transistor starts to turn on. lc87f0g08a no.a2304-23/31 consumption current characteristics at ta = -40 ? c to +85 ? c, v ss 1 = v ss 2 = 0v parameter symbol pin / remarks conditions specification v dd [v] min typ max unit normal mode consumption current (note 13-1) (note 13-2) iddop(1) v dd 1 ? fmcf=8mhz ceramic oscillation mode ? system clock set to 8mhz mode ? internal low-/medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/1 2.2 to 5.5 3.8 5.2 ma 2.2 to 3.6 2.2 2.9 iddop(2) ? fmcf=4mhz ceramic oscillation mode ? system clock set to 4mhz mode ? internal low-/medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/1 1.8 to 5.5 2.1 3.5 1.8 to 3.6 1.1 1.7 iddop(3) ? fsx?tal=32.768khz crystal oscillation mode ? internal low-speed rc oscillation stopped ? system clock set to internal medium-speed rc oscillation mode ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/2 1.8 to 5.5 0.23 0.39 1.8 to 3.6 0.13 0.19 iddop(4) ? fsx?tal=32.768khz crystal oscillation mode ? internal low-/medium-speed rc oscillation stopped ? system clock set to internal high-speed rc oscillation mode ? frequency division ratio set to 1/1 1.8 to 5.5 2.7 3.6 1.8 to 3.6 1.7 2.3 iddop(5) ? external oscillation fsx?tal/fmcf stopped ? system clock set to internal low-speed rc oscillation mode ? internal medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/1 1.8 to 5.5 10 42 ? a 1.8 to 3.6 6 21 iddop(6) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz mode ? internal low-/medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/2 1.8 to 5.5 46 101 1.8 to 3.6 16 40 continued on next page. lc87f0g08a no.a2304-24/31 continued from preceding page. parameter symbol pin / remarks conditions specification v dd [ v] min typ max unit halt mode consumption current (note 13-1) (note 13-2) iddhalt(1) v dd 1 halt mode ? fmcf=8mhz ceramic oscillation mode ? system clock set to 8mhz mode ? internal low-/medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/1 2.2 to 5.5 2.0 3.2 ma 2.2 to 3.6 1.0 1.6 iddhalt(2) halt mode ? fmcf=4mhz ceramic oscillation mode ? system clock set to 4mhz mode ? internal low-/medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/1 1.8 to 5.5 1.2 2.4 1.8 to 3.6 0.5 1.0 iddhalt(3) halt mode ? fsx?tal=32.768khz crystal oscillation mode ? internal low-speed rc oscillation stopped ? system clock set to internal medium-speed rc oscillation mode ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/2 1.8 to 5.5 0.12 0.25 1.8 to 3.6 0.06 0.11 iddhalt(4) halt mode ? fsx?tal=32.768khz crystal oscillation mode ? internal low-/medium-speed rc oscillation stopped ? system clock set to internal high-speed rc oscillation mode ? frequency division ratio set to 1/1 1.8 to 5.5 1.1 1.7 1.8 to 3.6 0.7 1.0 iddhalt(5) halt mode ? external oscillation fsx?tal/fmcf stopped ? system clock set to internal low-speed rc oscillation mode ? internal medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/1 1.8 to 5.5 3.8 37 ? a 1.8 to 3.6 2.4 17 iddhalt(6) halt mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz mode ? internal low-/medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/2 1.8 to 5.5 42 97 1.8 to 3.6 13 38 hold mode consumption current (note 13-1) (note 13-2) iddhold(1) v dd 1 hold mode 1.8 to 5.5 0.023 33.2 ? a 1.8 to 3.6 0.012 14.2 iddhold(2) hold mode ? lvd option selected 1.8 to 5.5 1.09 26.9 1.8 to 3.6 0.86 11.8 timer hold mode consumption current (note 13-1) (note 13-2) iddhold(3) v dd 1 timer hold mode ? fsx?tal=32.768khz crystal oscillation mode 1.8 to 5.5 39 94 1.8 to 3.6 12 36 iddhold(4) timer hold mode ? fmsrc=30khz internal low-speed rc oscillation mode 1.8 to 5.5 0.63 34 1.8 to 3.6 0.53 15 note 13-1: the consumption current value includes none of the currents that flow into the output transistors and internal pull-up resistors. note 13-2: unless otherwise specified, the consumption current for the lvd circuit is not included. lc87f0g08a no.a2304-25/31 f-rom programming characteristics at ta = +10 ? c to +55 ? c, v ss 1 = v ss 2 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? excluding power dissipation in the microcontroller block 2.2 to 5.5 5 10 ma programming time tfw(1) ? erasing time 2.2 to 5.5 20 30 ms tfw(2) ? programming time 40 60 ? s lc87f0g08a no.a2304-26/31 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator ? murata manufacturing co., ltd. nominal frequency type oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rf [ ? ] rd [ ? ] typ [ms] max [ms] 12mhz smd cstce12m0g52-r0 (10) ( 10) open 680 2.6 to 5.5 0.02 0.3 c1 and c2 integrated type 8mhz smd cstce8m00g52-r0 (10) ( 10) open 1k 2.1 to 5.5 0.02 0.3 4mhz smd cstcr4m00g53-r0 (15) (15) open 1.5k 1.8 to 5.5 0.03 0.45 characteristics of a sample subs ystem clock oscillation circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a sanyo- designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cloc k oscillator circuit that uses a crystal oscillator ? epson toyocom nominal frequency type oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rf [ ? ] rd [ ? ] typ [ms] max [ms] 32.768khz smd mc-306 9 9 open 330k 1.8 to 5.5 1.4 4.0 applicable cl value = 7.0pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized in the following cases (see figure 3): ? till the oscillation gets stabilized after the instruction fo r starting the subclock oscillation circuit is executed ? till the oscillation gets stabilized after the hold mode is released. note: the components that are in volved in oscillation should be placed as close to the ic an d to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf/xt oscillator circuit figure 2 ac timing measurement point rf rd cf1/xt1 cf2/xt2 c2 cf/x?tal c1 0.5v dd lc87f0g08a no.a2304-27/31 reset time and oscillation stabilization time hold release signal and oscillation stabilization time note: when an external oscillation circuit is selected. figure 3 oscillation stabilization time power supply res internal medium speed rc oscillation cf1, cf2 operating mode reset time unpredictable reset instruction execution v dd operating v dd lower limit 0v tmscf/tmsx?tal internal medium speed rc oscillation or internal low speed rc oscillation cf1, cf2 (note) hold reset signal hold release signal absent tmscf/tmsx?tal hold halt hold release signal valid state lc87f0g08a no.a2304-28/31 figure 4 sample reset circuit figure 5 serial i/o waveform figure 6 pulse input timing signal waveform c res v dd r res res note: the external circuit for reset may vary depending on the usage of por and lvd. see ?reset function? in the user's manual. tpil tpih di0 di7 di2 di3 di4 di5 di6 do0 do7 do2 do3 do4 do5 do6 di1 do1 sioclk: datain: dataout: dataout: datain: siocl tsck tsckl tsckh thdi tsdi tddo lc87f0g08a no.a2304-29/31 figure 7 10 ? /20 ? amplifier characteristics (a) 1) when p01/apip is 0v, p00/apim ? 0v. 2) when p00/apim is 0v, p01/apip ? 0v. (b) 1) when p00/apim is 0v, p01/apip ? 0v. 2) when p01/apip is 0v, p00/apim ? 0v. 1) p00/apim input 2) p01/apipinput vref ampout p u t 0 0v apgain ( a ) vref ampout p u t 0 1) p01/apipinput 2) p00/apiminput 0v apgain ( b ) -vapful +vapful vapio vapio lc87f0g08a no.a2304-30/31 figure 8 example of por only (lvd deselected) mode waveforms (at reset pin with r res pull-up resistor only) ? the por function generates a reset only when the power voltage goes up from the v ss level. ? no stable reset will be generated if power is turned on again when the power level does not go down to the v ss level as shown in (a). if such a case is an ticipated, use the lvd function together with the por function or implement an external reset circuit as shown below. ? a reset is generated only when the power level goes down to the v ss level as shown in (b) and power is turned on again after this condition continues for 100 ? s or longer. figure 9 example of por + lvd mode waveforms (at reset pin with r res pull-up resistor only) ? resets are generated both when power is tu rned on and when the power level lowers. ? a hysteresis width (lvhys) is provided to prevent the repetitions of reset releas e and entry cycles near the detection level . por release voltage (porrl) v dd res reset unknown area ( pouks ) (a) (b) reset period reset period 100 ? lc87f0g08a no.a2304-31/31 figure 10 minimum low voltage detection width (example of voltage sag/fluctuation waveform) ordering information device package shipping (qty / packing) lc87f0g08auja-ah ssop24(225mil) (pb-free / halogen free) 2000 / tape & reel LC87F0G08AUJA-FH ssop24(225mil) (pb-free / halogen free) 2000 / tape & reel lc87f0g08auja-zh ssop24(225mil) (pb-free / halogen free) 1400 / fan-fold v dd lvd detect voltage tlvdw v ss lvd release voltage lvdet-0.5v on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liab ility arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use a s components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applica tion in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for an y such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and dis tributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona linjuryor death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale i n any manner. p s |
Price & Availability of LC87F0G08AUJA-FH
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |